Hello,
On Wed, Oct 26, 2022 at 04:17:55PM +0200, Uwe Kleine-König wrote:
> On Wed, Oct 26, 2022 at 11:13:04AM +0100, Jon Hunter wrote:
> > For the case where dev_pm_opp_set_rate() is called to set the PWM clock
> > rate, the requested rate is calculated as ...
> >
> > required_clk_rate = (NSEC_PER_SEC / period_ns) << PWM_DUTY_WIDTH;
> >
> > The above calculation may lead to rounding errors because the
> > NSEC_PER_SEC is divided by 'period_ns' before applying the
> > PWM_DUTY_WIDTH multiplication factor. For example, if the period is
> > 45334ns, the above calculation yields a rate of 5646848Hz instead of
> > 5646976Hz. Fix this by applying the multiplication factor before
> > dividing and using the DIV_ROUND_UP macro which yields the expected
> > result of 5646976Hz.
> >
> > Fixes: 1d7796bdb63a ("pwm: tegra: Support dynamic clock frequency configuration")
> > Signed-off-by: Jon Hunter <jonathanh@xxxxxxxxxx>
> > ---
> > drivers/pwm/pwm-tegra.c | 4 ++--
> > 1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c
> > index dad9978c9186..8a33c500f93b 100644
> > --- a/drivers/pwm/pwm-tegra.c
> > +++ b/drivers/pwm/pwm-tegra.c
> > @@ -145,8 +145,8 @@ static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
> > * source clock rate as required_clk_rate, PWM controller will
> > * be able to configure the requested period.
> > */
> > - required_clk_rate =
> > - (NSEC_PER_SEC / period_ns) << PWM_DUTY_WIDTH;
> > + required_clk_rate = DIV_ROUND_UP_ULL((NSEC_PER_SEC << PWM_DUTY_WIDTH),
> > + period_ns);
>
> This also has the nice side effect that required_clk_rate doesn't become
> zero any more for big period_ns values.
>
> Reviewed-by: Uwe Kleine-König <u.kleine-koenig@xxxxxxxxxxxxxx>
I just noticed you could drop a pair of parenthesis in the first parameter
to DIV_ROUND_UP_ULL.
Best regards
Uwe
--
Pengutronix e.K. | Uwe Kleine-König |
Industrial Linux Solutions | https://www.pengutronix.de/ |
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