Currently, the default setting is that CLKREQ signal of a Root Port is internally overridden to '0' to enable REFCLK to flow out to the slot. It is observed that one of the PCIe switches (case in point Broadcom PCIe Gen4 switch) is propagating the CLKREQ signal of the root port to the downstream side of the switch and expecting the endpoints to pull it low so that it (PCIe switch) can give out the REFCLK although the Switch as such doesn't support CLK-PM or ASPM-L1SS. So, as a workaround, this patch drives the CLKREQ of the Root Port itself low to avoid link up issues between PCIe switch downstream port and endpoints. This is not a wrong thing to do after all the CLKREQ is anyway being overridden to '0' internally and now it is just that the same is being propagated outside also. Signed-off-by: Vidya Sagar <vidyas@xxxxxxxxxx> --- V3: * Reworded the commit message V2: * None drivers/pci/controller/dwc/pcie-tegra194.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index d7ab33931de4..a33c86e3de9d 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -47,6 +47,7 @@ #define APPL_PINMUX_CLKREQ_OVERRIDE BIT(3) #define APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE_EN BIT(4) #define APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE BIT(5) +#define APPL_PINMUX_CLKREQ_DEFAULT_VALUE BIT(13) #define APPL_CTRL 0x4 #define APPL_CTRL_SYS_PRE_DET_STATE BIT(6) @@ -1510,6 +1511,7 @@ static int tegra_pcie_config_controller(struct tegra_pcie_dw *pcie, val = appl_readl(pcie, APPL_PINMUX); val |= APPL_PINMUX_CLKREQ_OVERRIDE_EN; val &= ~APPL_PINMUX_CLKREQ_OVERRIDE; + val &= ~APPL_PINMUX_CLKREQ_DEFAULT_VALUE; appl_writel(pcie, val, APPL_PINMUX); } -- 2.17.1
