Hi Will,
> -----Original Message-----
> From: Will Deacon <will@xxxxxxxxxx>
> Sent: 22 September 2022 14:53
> To: Besar Wicaksono <bwicaksono@xxxxxxxxxx>
> Subject: Re: [PATCH v4 1/2] perf: arm_cspmu: Add support for ARM CoreSight
> PMU driver
[...]
> > +/* Check if PMU supports 64-bit single copy atomic. */ static inline
> > +bool supports_64bit_atomics(const struct arm_cspmu *cspmu) {
> > + return CHECK_APMT_FLAG(cspmu->apmt_node->flags, ATOMIC, SUPP); }
>
> Is this just there because the architecture permits it, or are folks
> actually hanging these things off 32-bit MMIO buses on arm64 SoCs?
The CPU PMU is often exposed on the CoreSight APB bus (32-bit), and although this driver wouldn't normally be used to access that PMU, I wouldn't rule out similar legacy APB and AHB interfaces being used for other PMUs. A further issue is that the CoreSight PMU model includes a number of 32-bit control registers.
Since issue H.a there is an alternative 64-bit native PMU interface described in the Arm ARM, which must support 64-bit atomic accesses. You might expect this to also appear in CoreSight PMU at some point soon. That would need some additional updates to this driver because all the registers are now 64 bit, which changes some offsets.
Regards,
Mike.
