On Wed, Mar 16, 2022 at 03:14:45PM +0530, Aniruddha Rao wrote: > The default parent for SDMMC1/3 clock sources can provide maximum frequency > of 136MHz for SDR104 mode. > Update parent clock source for SDMMC1/SDMMC3 instances > to increase the output clock frequency to 195MHz and improve the perf. > > Signed-off-by: Aniruddha Rao <anrao@xxxxxxxxxx> > --- > arch/arm64/boot/dts/nvidia/tegra194.dtsi | 10 ++++++++++ > 1 file changed, 10 insertions(+) Applied, thanks. Thierry
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