Hi Robert,
On Tue, Mar 15 2022, Robert Marko wrote:
> On Fri, Feb 11, 2022 at 5:06 PM Lorenzo Pieralisi
> <lorenzo.pieralisi@xxxxxxx> wrote:
>>
>> On Mon, Feb 07, 2022 at 04:51:23PM +0200, Baruch Siach wrote:
>> > This series adds support for the single PCIe lane on IPQ6018 SoCs. The code is
>> > ported from downstream Codeaurora v5.4 kernel. The main difference from
>> > downstream code is the split of PCIe registers configuration from .init to
>> > .post_init, since it requires phy_power_on().
>> >
>> > Tested on IPQ6010 based hardware.
[snip]
>> >
>> > Baruch Siach (2):
>> > PCI: dwc: tegra: move GEN3_RELATED DBI register to common header
>> > PCI: qcom: Define slot capabilities using PCI_EXP_SLTCAP_*
>> >
>> > Selvam Sathappan Periakaruppan (1):
>> > PCI: qcom: Add IPQ60xx support
>> >
>> > drivers/pci/controller/dwc/pcie-designware.h | 7 +
>> > drivers/pci/controller/dwc/pcie-qcom.c | 155 ++++++++++++++++++-
>> > drivers/pci/controller/dwc/pcie-tegra194.c | 6 -
>> > 3 files changed, 160 insertions(+), 8 deletions(-)
>>
>> Bjorn, Andy,
>>
>> Can you ACK please if this series is ready to be merged ?
>
> This would also help the IPQ8074 which has the same controller for the
> Gen3 port.
>
> I have been using this for OpenWrt for a while and it works.
Thanks for your test report.
It would be nice to have a formal Tested-by for the pcie-qcom.c
patch. It might help to push the patch forward.
Can you also share the device-tree part? I'll add it to this series in
case it needs a respin.
Thanks,
baruch
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