On 02/03/2022 18:51, Rob Herring wrote: > On Wed, Mar 02, 2022 at 02:13:27PM +0530, Ashish Mhetre wrote: >> >From tegra186 onwards, memory controller support multiple channels. >> Reg items are updated with address and size of these channels. >> Tegra186 has overall 5 memory controller channels. Tegra194 and tegra234 >> have overall 17 memory controller channels each. >> There is 1 reg item for memory controller stream-id registers. >> So update the reg maxItems to 18 in tegra186 devicetree documentation. > > Some of this needs to be in 'description' for 'reg'. > >> >> Signed-off-by: Ashish Mhetre <amhetre@xxxxxxxxxx> >> --- >> .../devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> >> diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml >> index 13c4c82..eb7ed00 100644 >> --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml >> +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml >> @@ -35,7 +35,7 @@ properties: >> >> reg: >> minItems: 1 >> - maxItems: 3 >> + maxItems: 18 >> ...and with "if:" block constraining these on different hardware. Best regards, Krzysztof
