On 14/12/2021 13:36, Prathamesh Shete wrote:
> When CMD13 is sent after switching to HS400ES mode, the bus
> is operating at either MMC_HIGH_26_MAX_DTR or MMC_HIGH_52_MAX_DTR.
> To meet Tegra SDHCI requirement at HS400ES mode, force SDHCI
> interface clock to MMC_HS200_MAX_DTR (200 MHz) so that host
> controller CAR clock and the interface clock are rate matched.
>
> Signed-off-by: Prathamesh Shete <pshete@xxxxxxxxxx>
Acked-by: Adrian Hunter <adrian.hunter@xxxxxxxxx>
> ---
> drivers/mmc/host/sdhci-tegra.c | 43 ++++++++++++++++++++--------------
> 1 file changed, 26 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c
> index 387ce9cdbd7c..7be6674eebd5 100644
> --- a/drivers/mmc/host/sdhci-tegra.c
> +++ b/drivers/mmc/host/sdhci-tegra.c
> @@ -354,23 +354,6 @@ static void tegra_sdhci_set_tap(struct sdhci_host *host, unsigned int tap)
> }
> }
>
> -static void tegra_sdhci_hs400_enhanced_strobe(struct mmc_host *mmc,
> - struct mmc_ios *ios)
> -{
> - struct sdhci_host *host = mmc_priv(mmc);
> - u32 val;
> -
> - val = sdhci_readl(host, SDHCI_TEGRA_VENDOR_SYS_SW_CTRL);
> -
> - if (ios->enhanced_strobe)
> - val |= SDHCI_TEGRA_SYS_SW_CTRL_ENHANCED_STROBE;
> - else
> - val &= ~SDHCI_TEGRA_SYS_SW_CTRL_ENHANCED_STROBE;
> -
> - sdhci_writel(host, val, SDHCI_TEGRA_VENDOR_SYS_SW_CTRL);
> -
> -}
> -
> static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask)
> {
> struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> @@ -791,6 +774,32 @@ static void tegra_sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
> }
> }
>
> +static void tegra_sdhci_hs400_enhanced_strobe(struct mmc_host *mmc,
> + struct mmc_ios *ios)
> +{
> + struct sdhci_host *host = mmc_priv(mmc);
> + u32 val;
> +
> + val = sdhci_readl(host, SDHCI_TEGRA_VENDOR_SYS_SW_CTRL);
> +
> + if (ios->enhanced_strobe) {
> + val |= SDHCI_TEGRA_SYS_SW_CTRL_ENHANCED_STROBE;
> + /*
> + * When CMD13 is sent from mmc_select_hs400es() after
> + * switching to HS400ES mode, the bus is operating at
> + * either MMC_HIGH_26_MAX_DTR or MMC_HIGH_52_MAX_DTR.
> + * To meet Tegra SDHCI requirement at HS400ES mode, force SDHCI
> + * interface clock to MMC_HS200_MAX_DTR (200 MHz) so that host
> + * controller CAR clock and the interface clock are rate matched.
> + */
> + tegra_sdhci_set_clock(host, MMC_HS200_MAX_DTR);
> + } else {
> + val &= ~SDHCI_TEGRA_SYS_SW_CTRL_ENHANCED_STROBE;
> + }
> +
> + sdhci_writel(host, val, SDHCI_TEGRA_VENDOR_SYS_SW_CTRL);
> +}
> +
> static unsigned int tegra_sdhci_get_max_clock(struct sdhci_host *host)
> {
> struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> -- 2.17.1
>
