On Wed, Sep 22, 2021 at 11:29:21AM +0200, Bartosz Golaszewski wrote: > On Tue, Sep 7, 2021 at 9:32 AM Prathamesh Shete <pshete@xxxxxxxxxx> wrote: > > > > From: pshete <pshete@xxxxxxxxxx> > > > > Tegra19x supports 8 entries for GPIO controller. > > This change adds the required interrupt entires for all GPIO controllers. > > > > Signed-off-by: Prathamesh Shete <pshete@xxxxxxxxxx> > > --- > > arch/arm64/boot/dts/nvidia/tegra194.dtsi | 49 +++++++++++++++++++++++- > > 1 file changed, 47 insertions(+), 2 deletions(-) > > > > diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi > > index b7d532841390..c681a79c44ec 100644 > > --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi > > +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi > > @@ -34,11 +34,53 @@ > > reg = <0x2200000 0x10000>, > > <0x2210000 0x10000>; > > interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, > > <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, > > <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, > > <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, > > <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, > > - <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; > > + <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; > > #interrupt-cells = <2>; > > interrupt-controller; > > #gpio-cells = <2>; > > @@ -1273,7 +1315,10 @@ > > reg-names = "security", "gpio"; > > reg = <0xc2f0000 0x1000>, > > <0xc2f1000 0x1000>; > > - interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; > > + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; > > gpio-controller; > > #gpio-cells = <2>; > > interrupt-controller; > > -- > > 2.17.1 > > > > Prathamesh: what are the changes between the three versions of this > patch I have in my inbox? Please always include a brief list of > updates when resending. > > Thierry: does this make sense to you? Hi Bartosz, the following patches from me that you applied earlier: [PATCH 1/2] gpio: tegra186: Force one interrupt per bank [PATCH 2/2] gpio: tegra186: Support multiple interrupts per bank are replacements for patch 1 in this series, so that should no longer be needed. Patch 2 of this series (the DT change) I plan to pick up into the Tegra tree for v5.16. Thierry
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