On Fri, Sep 17, 2021 at 12:54 PM Thierry Reding <thierry.reding@xxxxxxxxx> wrote: > > From: Thierry Reding <treding@xxxxxxxxxx> > > Newer chips support up to 8 interrupts per bank, which can be useful to > balance the load and decrease latency. However, it also required a very > complicated interrupt routing to be set up. To keep things simple for > now, ensure that a single interrupt per bank is enforced, even if all > possible interrupts are described in device tree. > > Signed-off-by: Thierry Reding <treding@xxxxxxxxxx> > --- Applied, thanks! Bart
