From: Thierry Reding <treding@xxxxxxxxxx> Convert the old plain-text device tree bindings for the USB EHCI controller found on NVIDIA Tegra SoCs to the json-schema format. Signed-off-by: Thierry Reding <treding@xxxxxxxxxx> --- Changes in v2: - drop unneeded clock-names property - fix indentation issues .../bindings/usb/nvidia,tegra20-ehci.txt | 23 --- .../bindings/usb/nvidia,tegra20-ehci.yaml | 150 ++++++++++++++++++ 2 files changed, 150 insertions(+), 23 deletions(-) delete mode 100644 Documentation/devicetree/bindings/usb/nvidia,tegra20-ehci.txt create mode 100644 Documentation/devicetree/bindings/usb/nvidia,tegra20-ehci.yaml diff --git a/Documentation/devicetree/bindings/usb/nvidia,tegra20-ehci.txt b/Documentation/devicetree/bindings/usb/nvidia,tegra20-ehci.txt deleted file mode 100644 index f60785f73d3d..000000000000 --- a/Documentation/devicetree/bindings/usb/nvidia,tegra20-ehci.txt +++ /dev/null @@ -1,23 +0,0 @@ -Tegra SOC USB controllers - -The device node for a USB controller that is part of a Tegra -SOC is as described in the document "Open Firmware Recommended -Practice : Universal Serial Bus" with the following modifications -and additions : - -Required properties : - - compatible : For Tegra20, must contain "nvidia,tegra20-ehci". - For Tegra30, must contain "nvidia,tegra30-ehci". Otherwise, must contain - "nvidia,<chip>-ehci" plus at least one of the above, where <chip> is - tegra114, tegra124, tegra132, or tegra210. - - nvidia,phy : phandle of the PHY that the controller is connected to. - - clocks : Must contain one entry, for the module clock. - See ../clocks/clock-bindings.txt for details. - - resets : Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. - - reset-names : Must include the following entries: - - usb - -Optional properties: - - nvidia,needs-double-reset : boolean is to be set for some of the Tegra20 - USB ports, which need reset twice due to hardware issues. diff --git a/Documentation/devicetree/bindings/usb/nvidia,tegra20-ehci.yaml b/Documentation/devicetree/bindings/usb/nvidia,tegra20-ehci.yaml new file mode 100644 index 000000000000..079cae44b8d9 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/nvidia,tegra20-ehci.yaml @@ -0,0 +1,150 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/usb/nvidia,tegra20-ehci.yaml#"; +$schema: "http://devicetree.org/meta-schemas/core.yaml#"; + +title: Device tree binding for NVIDIA Tegra USB controllers + +description: | + The device node for a USB controller that is part of a Tegra SOC is as + described in the document "Open Firmware Recommended Practice : Universal + Serial Bus". Modifications and additions are detailed in this document. + +maintainers: + - Thierry Reding <treding@xxxxxxxxxx> + - Jon Hunter <jonathanh@xxxxxxxxxx> + +properties: + compatible: + oneOf: + - items: + - enum: + - nvidia,tegra210-ehci + - nvidia,tegra124-ehci + - nvidia,tegra114-ehci + - const: nvidia,tegra30-ehci + - items: + - const: nvidia,tegra30-ehci + - items: + - const: nvidia,tegra20-ehci + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + phy_type: + $ref: /schemas/types.yaml#/definitions/string + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + reset-names: + items: + - const: usb + + nvidia,phy: + $ref: /schemas/types.yaml#/definitions/phandle + description: + phandle of the PHY that the controller is connected to + + nvidia,needs-double-reset: + type: boolean + description: + This must be set for some instances of the USB controller found on + Tegra20 that need to be reset twice due to some hardware issue. + +additionalProperties: false + +required: + - compatible + - reg + - interrupts + - clocks + - resets + - reset-names + - phy_type + - nvidia,phy + +examples: + - | + #include <dt-bindings/clock/tegra20-car.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + usb@c5000000 { + compatible = "nvidia,tegra20-ehci"; + reg = <0xc5000000 0x4000>; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + phy_type = "utmi"; + clocks = <&tegra_car TEGRA20_CLK_USBD>; + resets = <&tegra_car 22>; + reset-names = "usb"; + nvidia,needs-double-reset; + nvidia,phy = <&phy1>; + }; + + - | + #include <dt-bindings/clock/tegra30-car.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + usb@7d000000 { + compatible = "nvidia,tegra30-ehci"; + reg = <0x7d000000 0x4000>; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + phy_type = "utmi"; + clocks = <&tegra_car TEGRA30_CLK_USBD>; + resets = <&tegra_car 22>; + reset-names = "usb"; + nvidia,needs-double-reset; + nvidia,phy = <&phy1>; + }; + + - | + #include <dt-bindings/clock/tegra114-car.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + usb@7d000000 { + compatible = "nvidia,tegra114-ehci", "nvidia,tegra30-ehci"; + reg = <0x7d000000 0x4000>; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + phy_type = "utmi"; + clocks = <&tegra_car TEGRA114_CLK_USBD>; + resets = <&tegra_car 22>; + reset-names = "usb"; + nvidia,phy = <&phy1>; + }; + + - | + #include <dt-bindings/clock/tegra124-car.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + usb@7d000000 { + compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci"; + reg = <0x7d000000 0x4000>; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + phy_type = "utmi"; + clocks = <&tegra_car TEGRA124_CLK_USBD>; + resets = <&tegra_car 22>; + reset-names = "usb"; + nvidia,phy = <&phy1>; + }; + + - | + #include <dt-bindings/clock/tegra210-car.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + usb@7d000000 { + compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci"; + reg = <0x7d000000 0x4000>; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + phy_type = "utmi"; + clocks = <&tegra_car TEGRA210_CLK_USBD>; + resets = <&tegra_car 22>; + reset-names = "usb"; + nvidia,phy = <&phy1>; + }; -- 2.32.0
