Hi Mike, Stephen,
The following changes since commit 6efb943b8616ec53a5e444193dccf1af9ad627b5:
Linux 5.13-rc1 (2021-05-09 14:17:44 -0700)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux.git tags/for-5.14-clk
for you to fetch changes up to f13570e7e830ca4fbf4869015af8492b8918445e:
clk: tegra: tegra124-emc: Fix clock imbalance in emc_set_timing() (2021-06-02 11:08:00 +0200)
Thanks,
Thierry
----------------------------------------------------------------
clk: tegra: Changes for v5.14-rc1
This contains a few fixes across the board and adds stubs to allow
certain drivers to be compile-tested. One other notable change added
here is that clock enabling no longer deasserts the reset. Drivers are
now supposed to do that explicitly because doing it implicitly can get
in the way of certain power-up sequences.
----------------------------------------------------------------
Dmitry Osipenko (9):
clk: tegra30: Use 300MHz for video decoder by default
clk: tegra: Fix refcounting of gate clocks
clk: tegra: Ensure that PLLU configuration is applied properly
clk: tegra: Halve SCLK rate on Tegra20
clk: tegra: Don't allow zero clock rate for PLLs
clk: tegra: cclk: Handle thermal DIV2 CPU frequency throttling
clk: tegra: Mark external clocks as not having reset control
clk: tegra: Don't deassert reset on enabling clocks
clk: tegra: Add stubs needed for compile-testing
Yang Yingliang (1):
clk: tegra: tegra124-emc: Fix clock imbalance in emc_set_timing()
drivers/clk/tegra/clk-periph-gate.c | 80 +++++++++++++++----------
drivers/clk/tegra/clk-periph.c | 11 ++++
drivers/clk/tegra/clk-pll.c | 12 ++--
drivers/clk/tegra/clk-tegra-periph.c | 6 +-
drivers/clk/tegra/clk-tegra-super-cclk.c | 16 ++++-
drivers/clk/tegra/clk-tegra124-emc.c | 4 +-
drivers/clk/tegra/clk-tegra20.c | 6 +-
drivers/clk/tegra/clk-tegra30.c | 6 +-
drivers/clk/tegra/clk.h | 4 --
drivers/soc/tegra/pmc.c | 5 --
include/linux/clk/tegra.h | 100 ++++++++++++++++++++++++-------
11 files changed, 170 insertions(+), 80 deletions(-)
