From: Thierry Reding <treding@xxxxxxxxxx>
On Sun, 16 May 2021 19:30:32 +0300, Dmitry Osipenko wrote:
> This series fixes couple minor standalone problems of the Tegra clk
> driver and adds new features.
>
> Changelog:
>
> v8: - Replaced division with a shift, which was suggested by Michał Mirosław
> in a comment to "Handle thermal DIV2 CPU frequency throttling" v7 patch.
> Cortex A9 CPUs don't have hardware divider and shifting is a minor
> improvement here, nevertheless it's good to have it.
>
> [...]
Applied, thanks!
[1/9] clk: tegra30: Use 300MHz for video decoder by default
(no commit info)
[2/9] clk: tegra: Fix refcounting of gate clocks
(no commit info)
[3/9] clk: tegra: Ensure that PLLU configuration is applied properly
(no commit info)
[4/9] clk: tegra: Halve SCLK rate on Tegra20
(no commit info)
[5/9] clk: tegra: Don't allow zero clock rate for PLLs
(no commit info)
[6/9] clk: tegra: cclk: Handle thermal DIV2 CPU frequency throttling
(no commit info)
[7/9] clk: tegra: Mark external clocks as not having reset control
(no commit info)
[8/9] clk: tegra: Don't deassert reset on enabling clocks
(no commit info)
Best regards,
--
Thierry Reding <treding@xxxxxxxxxx>
