Re: [PATCH v4 3/6] dt-bindings: power: tegra: Add binding for core power domain

[Thierry Reding <thierry.reding@xxxxxxxxx>]

On Wed, Mar 24, 2021 at 02:01:29AM +0300, Dmitry Osipenko wrote:
> 24.03.2021 01:48, Rob Herring пишет:
> > On Sun, Mar 14, 2021 at 07:48:07PM +0300, Dmitry Osipenko wrote:
> >> All NVIDIA Tegra SoCs have a core power domain where majority of hardware
> >> blocks reside. Add binding for the core power domain.
> >>
> >> Signed-off-by: Dmitry Osipenko <digetx@xxxxxxxxx>
> >> ---
> >>  .../power/nvidia,tegra20-core-domain.yaml     | 51 +++++++++++++++++++
> >>  1 file changed, 51 insertions(+)
> >>  create mode 100644 Documentation/devicetree/bindings/power/nvidia,tegra20-core-domain.yaml
> >>
> >> diff --git a/Documentation/devicetree/bindings/power/nvidia,tegra20-core-domain.yaml b/Documentation/devicetree/bindings/power/nvidia,tegra20-core-domain.yaml
> >> new file mode 100644
> >> index 000000000000..4692489d780a
> >> --- /dev/null
> >> +++ b/Documentation/devicetree/bindings/power/nvidia,tegra20-core-domain.yaml
> >> @@ -0,0 +1,51 @@
> >> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> >> +%YAML 1.2
> >> +---
> >> +$id: http://devicetree.org/schemas/power/nvidia,tegra20-core-domain.yaml#
> >> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> >> +
> >> +title: NVIDIA Tegra Core Power Domain
> >> +
> >> +maintainers:
> >> +  - Dmitry Osipenko <digetx@xxxxxxxxx>
> >> +  - Jon Hunter <jonathanh@xxxxxxxxxx>
> >> +  - Thierry Reding <thierry.reding@xxxxxxxxx>
> >> +
> >> +allOf:
> >> +  - $ref: power-domain.yaml#
> >> +
> >> +properties:
> >> +  compatible:
> >> +    enum:
> >> +      - nvidia,tegra20-core-domain
> >> +      - nvidia,tegra30-core-domain
> >> +
> >> +  operating-points-v2:
> >> +    description:
> >> +      Should contain level, voltages and opp-supported-hw property.
> >> +      The supported-hw is a bitfield indicating SoC speedo or process
> >> +      ID mask.
> >> +
> >> +  "#power-domain-cells":
> >> +    const: 0
> >> +
> >> +  power-supply:
> >> +    description:
> >> +      Phandle to voltage regulator connected to the SoC Core power rail.
> >> +
> >> +required:
> >> +  - compatible
> >> +  - operating-points-v2
> >> +  - "#power-domain-cells"
> >> +  - power-supply
> >> +
> >> +additionalProperties: false
> >> +
> >> +examples:
> >> +  - |
> >> +    power-domain {
> >> +        compatible = "nvidia,tegra20-core-domain";
> >> +        operating-points-v2 = <&opp_table>;
> >> +        power-supply = <&regulator>;
> >> +        #power-domain-cells = <0>;
> > 
> > AFAICT, there's no way to access this 'hardware'?
> correct

To avoid exposing this "virtual" device in device tree, could this
instead be modelled as a child node of the PMC node? We already expose a
couple of generic power domains that way on Tegra210 and later, so
perhaps some of that infrastructure can be reused? I suppose given that
this is different from the standard powergate domains that we expose so
far, this may need a different implementation, but from a device tree
bindings point of view it could fit in with that.

Thierry

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