> Subject: Re: [PATCH v2 05/15] PCI: xilinx: Convert to MSI domains
>
> On Wed, 24 Mar 2021 13:56:16 +0000,
> Bharat Kumar Gogada <bharatku@xxxxxxxxxx> wrote:
>
> > > Thanks for that. Can you please try the following patch and let me
> > > know if it helps?
> > >
> > > Thanks,
> > >
> > > M.
> > >
> > > diff --git a/drivers/pci/controller/pcie-xilinx.c
> > > b/drivers/pci/controller/pcie- xilinx.c index
> > > ad9abf405167..14001febf59a 100644
> > > --- a/drivers/pci/controller/pcie-xilinx.c
> > > +++ b/drivers/pci/controller/pcie-xilinx.c
> > > @@ -194,8 +194,18 @@ static struct pci_ops xilinx_pcie_ops = {
> > >
> > > /* MSI functions */
> > >
> > > +static void xilinx_msi_top_irq_ack(struct irq_data *d) {
> > > + /*
> > > + * xilinx_pcie_intr_handler() will have performed the Ack.
> > > + * Eventually, this should be fixed and the Ack be moved in
> > > + * the respective callbacks for INTx and MSI.
> > > + */
> > > +}
> > > +
> > > static struct irq_chip xilinx_msi_top_chip = {
> > > .name = "PCIe MSI",
> > > + .irq_ack = xilinx_msi_top_irq_ack,
> > > };
> > >
> > > static int xilinx_msi_set_affinity(struct irq_data *d, const struct
> > > cpumask *mask, bool force) @@ -206,7 +216,7 @@ static int
> > > xilinx_msi_set_affinity(struct irq_data *d, const struct cpumask
> > > *mas static void xilinx_compose_msi_msg(struct irq_data *data, struct
> msi_msg *msg) {
> > > struct xilinx_pcie_port *pcie = irq_data_get_irq_chip_data(data);
> > > - phys_addr_t pa = virt_to_phys(pcie);
> > > + phys_addr_t pa = ALIGN_DOWN(virt_to_phys(pcie), SZ_4K);
> > >
> > > msg->address_lo = lower_32_bits(pa);
> > > msg->address_hi = upper_32_bits(pa); @@ -468,7 +478,7 @@ static
> > > int xilinx_pcie_init_irq_domain(struct
> > > xilinx_pcie_port *port)
> > >
> > > /* Setup MSI */
> > > if (IS_ENABLED(CONFIG_PCI_MSI)) {
> > > - phys_addr_t pa = virt_to_phys(port);
> > > + phys_addr_t pa = ALIGN_DOWN(virt_to_phys(port), SZ_4K);
> > >
> > > ret = xilinx_allocate_msi_domains(port);
> > > if (ret)
> > >
> > Thanks Marc.
> > With above patch now everything works fine, tested a Samsung NVMe SSD.
> > tst~# lspci
> > 00:00.0 PCI bridge: Xilinx Corporation Device 0706
> > 01:00.0 Non-Volatile memory controller: Samsung Electronics Co Ltd
> > NVMe SSD Controller 172Xa/172Xb (rev 01)
>
> Great, thanks for giving it a shot. Can I take this as a Tested-by:
> tag?
>
Yes.
Regards,
Bharat
