28.12.2020 18:49, Dmitry Osipenko пишет: > Display controller (DC) performs isochronous memory transfers, and thus, > has a requirement for a minimum memory bandwidth that shall be fulfilled, > otherwise framebuffer data can't be fetched fast enough and this results > in a DC's data-FIFO underflow that follows by a visual corruption. > > The Memory Controller drivers provide facility for memory bandwidth > management via interconnect API. Let's wire up the interconnect API > support to the DC driver in order to fix the distorted display output > on T30 Ouya, T124 TK1 and other Tegra devices. > > Tested-by: Peter Geis <pgwipeout@xxxxxxxxx> > Tested-by: Nicolas Chauvet <kwizart@xxxxxxxxx> > Signed-off-by: Dmitry Osipenko <digetx@xxxxxxxxx> > --- Thierry, I'm looking forward to yours review. Only DRM patches are left unmerged yet in this series.
