Enable CPU frequency and voltage scaling on all Tegra30 Cardhu board variants.
Signed-off-by: Dmitry Osipenko <digetx@xxxxxxxxx>
---
arch/arm/boot/dts/tegra30-cardhu-a04.dts | 48 ------------------------
arch/arm/boot/dts/tegra30-cardhu.dtsi | 40 ++++++++++++++++++--
2 files changed, 37 insertions(+), 51 deletions(-)
diff --git a/arch/arm/boot/dts/tegra30-cardhu-a04.dts b/arch/arm/boot/dts/tegra30-cardhu-a04.dts
index c1c0ca628af1..a11028b8b67b 100644
--- a/arch/arm/boot/dts/tegra30-cardhu-a04.dts
+++ b/arch/arm/boot/dts/tegra30-cardhu-a04.dts
@@ -2,8 +2,6 @@
/dts-v1/;
#include "tegra30-cardhu.dtsi"
-#include "tegra30-cpu-opp.dtsi"
-#include "tegra30-cpu-opp-microvolt.dtsi"
/* This dts file support the cardhu A04 and later versions of board */
@@ -92,50 +90,4 @@ vdd_bl2_reg: regulator@106 {
enable-active-high;
gpio = <&gpio TEGRA_GPIO(DD, 0) GPIO_ACTIVE_HIGH>;
};
-
- i2c@7000d000 {
- pmic: tps65911@2d {
- regulators {
- vddctrl_reg: vddctrl {
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <1125000>;
- regulator-coupled-with = <&vddcore_reg>;
- regulator-coupled-max-spread = <300000>;
- regulator-max-step-microvolt = <100000>;
-
- nvidia,tegra-cpu-regulator;
- };
- };
- };
-
- vddcore_reg: tps62361@60 {
- regulator-coupled-with = <&vddctrl_reg>;
- regulator-coupled-max-spread = <300000>;
- regulator-max-step-microvolt = <100000>;
-
- nvidia,tegra-core-regulator;
- };
- };
-
- cpus {
- cpu0: cpu@0 {
- cpu-supply = <&vddctrl_reg>;
- operating-points-v2 = <&cpu0_opp_table>;
- };
-
- cpu@1 {
- cpu-supply = <&vddctrl_reg>;
- operating-points-v2 = <&cpu0_opp_table>;
- };
-
- cpu@2 {
- cpu-supply = <&vddctrl_reg>;
- operating-points-v2 = <&cpu0_opp_table>;
- };
-
- cpu@3 {
- cpu-supply = <&vddctrl_reg>;
- operating-points-v2 = <&cpu0_opp_table>;
- };
- };
};
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi
index 788f16d2a0fa..309538bdcd66 100644
--- a/arch/arm/boot/dts/tegra30-cardhu.dtsi
+++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi
@@ -1,6 +1,8 @@
// SPDX-License-Identifier: GPL-2.0
#include <dt-bindings/input/input.h>
#include "tegra30.dtsi"
+#include "tegra30-cpu-opp.dtsi"
+#include "tegra30-cpu-opp-microvolt.dtsi"
/**
* This file contains common DT entry for all fab version of Cardhu.
@@ -273,9 +275,14 @@ vdd2_reg: vdd2 {
vddctrl_reg: vddctrl {
regulator-name = "vdd_cpu,vdd_sys";
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-coupled-with = <&vdd_core>;
+ regulator-coupled-max-spread = <300000>;
+ regulator-max-step-microvolt = <100000>;
regulator-always-on;
+
+ nvidia,tegra-cpu-regulator;
};
vio_reg: vio {
@@ -343,17 +350,22 @@ temperature-sensor@4c {
interrupts = <TEGRA_GPIO(CC, 2) IRQ_TYPE_LEVEL_LOW>;
};
- tps62361@60 {
+ vdd_core: tps62361@60 {
compatible = "ti,tps62361";
reg = <0x60>;
regulator-name = "tps62361-vout";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1500000>;
+ regulator-coupled-with = <&vddctrl_reg>;
+ regulator-coupled-max-spread = <300000>;
+ regulator-max-step-microvolt = <100000>;
regulator-boot-on;
regulator-always-on;
ti,vsel0-state-high;
ti,vsel1-state-high;
+
+ nvidia,tegra-core-regulator;
};
};
@@ -425,6 +437,28 @@ clk32k_in: clock@0 {
#clock-cells = <0>;
};
+ cpus {
+ cpu0: cpu@0 {
+ cpu-supply = <&vddctrl_reg>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ };
+
+ cpu1: cpu@1 {
+ cpu-supply = <&vddctrl_reg>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ };
+
+ cpu2: cpu@2 {
+ cpu-supply = <&vddctrl_reg>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ };
+
+ cpu3: cpu@3 {
+ cpu-supply = <&vddctrl_reg>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ };
+ };
+
panel: panel {
compatible = "chunghwa,claa101wb01";
ddc-i2c-bus = <&panelddc>;
--
2.29.2
