On Tue, Jan 12, 2021 at 03:27:23PM +0300, Dmitry Osipenko wrote: > Higher SCLK rates on Tegra20 require high core voltage. The higher > clock rate may have a positive performance effect only for AHB DMA > transfers and AVP CPU, but both aren't used by upstream kernel at all. > Halve SCLK rate on Tegra20 in order to remove the high core voltage > requirement. > > Signed-off-by: Dmitry Osipenko <digetx@xxxxxxxxx> > --- > drivers/clk/tegra/clk-tegra20.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) Acked-by: Thierry Reding <treding@xxxxxxxxxx>
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