On Fri, Jan 08, 2021 at 01:59:12PM +0000, Peter Geis wrote: > Current implementation defaults the hda clocks to clk_m. This causes hda > to run too slow to operate correctly. Fix this by defaulting to pll_p and > setting the frequency to the correct rate. > > This matches upstream t124 and downstream t30. > > Acked-by: Jon Hunter <jonathanh@xxxxxxxxxx> > Tested-by: Ion Agorria <ion@xxxxxxxxxxx> > Signed-off-by: Peter Geis <pgwipeout@xxxxxxxxx> > --- > drivers/clk/tegra/clk-tegra30.c | 2 ++ > 1 file changed, 2 insertions(+) Acked-by: Thierry Reding <treding@xxxxxxxxxx>
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