Re: [PATCH v2] xhci: tegra: Delay for disabling LFPS detector

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On 8.1.2021 8.41, JC Kuo wrote:
> Occasionally, we are seeing some SuperSpeed devices resumes right after
> being directed to U3. This commits add 500us delay to ensure LFPS
> detector is disabled before sending ACK to firmware.
> 
> [   16.099363] tegra-xusb 70090000.usb: entering ELPG
> [   16.104343] tegra-xusb 70090000.usb: 2-1 isn't suspended: 0x0c001203
> [   16.114576] tegra-xusb 70090000.usb: not all ports suspended: -16
> [   16.120789] tegra-xusb 70090000.usb: entering ELPG failed
> 
> The register write passes through a few flop stages of 32KHz clock domain.
> NVIDIA ASIC designer reviewed RTL and suggests 500us delay.
> 
> Cc: stable@xxxxxxxxxxxxxxx
> Signed-off-by: JC Kuo <jckuo@xxxxxxxxxx>
> ---
>  drivers/usb/host/xhci-tegra.c | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> changes in v2: 
>     describes how 500us was determined in commit message
>     cc stable@xxxxxxxxxxxxxxx
> 

Thanks, added.

-Mathias




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