From: Pankaj Dubey <pankaj.dubey@xxxxxxxxxxx>
As part of dw_pcie_setup(), PHYs which are compliant to ZRX-DC
specification are already handled based on "phy-zrxdc-compliant" property
in PCIe PHY DT node. So, instead of handling ZRX-DC compliant settings in
each platform driver, remove this driver specific code.
Signed-off-by: Anvesh Salveru <anvesh.salveru@xxxxxxxxx>
Signed-off-by: Pankaj Dubey <pankaj.dubey@xxxxxxxxxxx>
Signed-off-by: Shradha Todi <shradha.t@xxxxxxxxxxx>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@xxxxxxx>
Cc: Andrew Murray <andrew.murray@xxxxxxx>
Cc: Bjorn Helgaas <bhelgaas@xxxxxxxxxx>
Cc: Vidya Sagar <vidyas@xxxxxxxxxx>
Cc: Jonathan Hunter <jonathanh@xxxxxxxxxx>
---
drivers/pci/controller/dwc/pcie-tegra194.c | 17 ++++++++---------
1 file changed, 8 insertions(+), 9 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index 6fa216e..50e85e5 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -194,7 +194,6 @@
#define GEN3_EQ_CONTROL_OFF_FB_MODE_MASK GENMASK(3, 0)
#define GEN3_RELATED_OFF 0x890
-#define GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL BIT(0)
#define GEN3_RELATED_OFF_GEN3_EQ_DISABLE BIT(16)
#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT 24
#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK GENMASK(25, 24)
@@ -899,10 +898,6 @@ static int tegra_pcie_dw_host_init(struct pcie_port *pp)
disable_aspm_l12(pcie);
}
- val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF);
- val &= ~GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL;
- dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val);
-
if (pcie->update_fc_fixup) {
val = dw_pcie_readl_dbi(pci, CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF);
val |= 0x1 << CFG_TIMER_CTRL_ACK_NAK_SHIFT;
@@ -1752,10 +1747,6 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie)
disable_aspm_l12(pcie);
}
- val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF);
- val &= ~GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL;
- dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val);
-
pcie->pcie_cap_base = dw_pcie_find_capability(&pcie->pci,
PCI_CAP_ID_EXP);
clk_set_rate(pcie->core_clk, GEN4_CORE_CLK_FREQ);
@@ -1958,6 +1949,7 @@ static int tegra_pcie_dw_probe(struct platform_device *pdev)
{
const struct tegra_pcie_dw_of_data *data;
struct device *dev = &pdev->dev;
+ unsigned int phy_zrxdc_count;
struct resource *atu_dma_res;
struct tegra_pcie_dw *pcie;
struct pcie_port *pp;
@@ -2066,8 +2058,15 @@ static int tegra_pcie_dw_probe(struct platform_device *pdev)
dev_err(dev, "Failed to get PHY: %d\n", ret);
return ret;
}
+ if (phy_property_present(phys[i], "phy-zrxdc-compliant"))
+ phy_zrxdc_count++;
}
+ if ((pcie->phy_count) && (pcie->phy_count == phy_zrxdc_count))
+ pci->phy_zrxdc_compliant = true;
+ else
+ pci->phy_zrxdc_compliant = false;
+
pcie->phys = phys;
atu_dma_res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
--
2.7.4
