Re: [PATCH] xhci: tegra: Delay for disabling LFPS detector

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On 12/19/20 12:53 AM, Greg KH wrote:
> On Sat, Dec 19, 2020 at 12:42:34AM +0800, JC Kuo wrote:
>> Occasionally, we are seeing some SuperSpeed devices resumes right after
>> being directed to U3. This commits add 500us delay to ensure LFPS
>> detector is disabled before sending ACK to firmware.
>>
>> [   16.099363] tegra-xusb 70090000.usb: entering ELPG
>> [   16.104343] tegra-xusb 70090000.usb: 2-1 isn't suspended: 0x0c001203
>> [   16.114576] tegra-xusb 70090000.usb: not all ports suspended: -16
>> [   16.120789] tegra-xusb 70090000.usb: entering ELPG failed
>>
>> Signed-off-by: JC Kuo <jckuo@xxxxxxxxxx>
>> ---
>>  drivers/usb/host/xhci-tegra.c | 6 ++++++
>>  1 file changed, 6 insertions(+)
>>
>> diff --git a/drivers/usb/host/xhci-tegra.c b/drivers/usb/host/xhci-tegra.c
>> index 934be1686352..20cdc11f7dc6 100644
>> --- a/drivers/usb/host/xhci-tegra.c
>> +++ b/drivers/usb/host/xhci-tegra.c
>> @@ -623,6 +623,12 @@ static void tegra_xusb_mbox_handle(struct tegra_xusb *tegra,
>>  								     enable);
>>  			if (err < 0)
>>  				break;
>> +
>> +			/*
>> +			 * wait 500us for LFPS detector to be disabled before sending ACK
>> +			 */
>> +			if (!enable)
>> +				usleep_range(500, 1000);
> 
> Where does the magic 500us come from?  How can we "know" this is long
> enough?

Hi Greg,
The register write passes through a few flop stages of 32KHz clock domain. Our
ASIC designer reviewed RTL and suggests 500us delay. It has also been verified
thoroughly.

Thanks,
JC

> 
> thanks,
> 
> greg k-h
> 



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