[+cc Jingoo, Gustavo]
On Thu, Dec 03, 2020 at 07:04:51PM +0530, Vidya Sagar wrote:
> PCIe cards like Marvell SATA controller and some of the Samsung NVMe
> drives don't support taking the link to L2 state. When the link doesn't
> go to L2 state, Tegra194 requires the LTSSM to be disabled to allow PHY
> to start the next link up process cleanly during suspend/resume sequence.
> Failing to disable LTSSM results in the PCIe link not coming up in the
> next resume cycle.
Is this a Tegra194-specific issue, or will other DWC-based controllers
need a similar change?
> Tested-by: Thierry Reding <treding@xxxxxxxxxx>
> Signed-off-by: Vidya Sagar <vidyas@xxxxxxxxxx>
> Acked-by: Thierry Reding <treding@xxxxxxxxxx>
> ---
> V5:
> * Added Tested-by and Acked-by from Thierry Reding
>
> V4:
> * New patch in this series
>
> drivers/pci/controller/dwc/pcie-tegra194.c | 16 +++++++++-------
> 1 file changed, 9 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
> index f4109d71f20b..5597b2a49598 100644
> --- a/drivers/pci/controller/dwc/pcie-tegra194.c
> +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
> @@ -1506,6 +1506,14 @@ static void tegra_pcie_dw_pme_turnoff(struct tegra_pcie_dw *pcie)
> data &= ~APPL_PINMUX_PEX_RST;
> appl_writel(pcie, data, APPL_PINMUX);
>
> + /*
> + * Some cards do not go to detect state even after de-asserting
> + * PERST#. So, de-assert LTSSM to bring link to detect state.
> + */
> + data = readl(pcie->appl_base + APPL_CTRL);
> + data &= ~APPL_CTRL_LTSSM_EN;
> + writel(data, pcie->appl_base + APPL_CTRL);
> +
> err = readl_poll_timeout_atomic(pcie->appl_base + APPL_DEBUG,
> data,
> ((data &
> @@ -1513,14 +1521,8 @@ static void tegra_pcie_dw_pme_turnoff(struct tegra_pcie_dw *pcie)
> APPL_DEBUG_LTSSM_STATE_SHIFT) ==
> LTSSM_STATE_PRE_DETECT,
> 1, LTSSM_TIMEOUT);
> - if (err) {
> + if (err)
> dev_info(pcie->dev, "Link didn't go to detect state\n");
> - } else {
> - /* Disable LTSSM after link is in detect state */
> - data = appl_readl(pcie, APPL_CTRL);
> - data &= ~APPL_CTRL_LTSSM_EN;
> - appl_writel(pcie, data, APPL_CTRL);
> - }
> }
> /*
> * DBI registers may not be accessible after this as PLL-E would be
> --
> 2.17.1
>
