On Thu, 17 Sep 2020 at 12:43, Thierry Reding <thierry.reding@xxxxxxxxx> wrote: > > On Tue, Sep 15, 2020 at 04:28:03PM -0700, Nicolin Chen wrote: > > According to Tegra210 TRM, the default value of TLB_ACTIVE_LINES > > field of register MC_SMMU_TLB_CONFIG_0 is 0x30. So num_tlb_lines > > should be 48 (0x30) rather than 32 (0x20). > > > > Signed-off-by: Nicolin Chen <nicoleotsuka@xxxxxxxxx> > > --- > > drivers/memory/tegra/tegra210.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > Please send this as part of a series including: > > https://patchwork.ozlabs.org/project/linux-tegra/patch/20200916002359.10823-1-nicoleotsuka@xxxxxxxxx/ > > Adding Joerg for visibility. From the Tegra side: > > Acked-by: Thierry Reding <treding@xxxxxxxxxx> So basically applying this one alone breaks existing platforms and makes history non-bisectable... Nicolin, the bisectability is important requirement so you must always mention the dependencies between patches. Best regards, Krzysztof
