The default parent for all MMCs is PLLP, which is running at 408MHz on
Tegra30 and 50MHz clock can't be derived from PLLP. The maximum SDIO
clock rate is 50MHz, but this rate isn't achievable using PLLP.
Let's switch the WiFi MMC clk parent to PLLC in order to get true 50MHz.
This patch doesn't fix any problems, it's just a minor improvement.
Signed-off-by: Dmitry Osipenko <digetx@xxxxxxxxx>
---
arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi
index 903457292c04..21387a91c40f 100644
--- a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi
+++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi
@@ -976,6 +976,11 @@ mmc@78000400 {
#address-cells = <1>;
#size-cells = <0>;
+ assigned-clocks = <&tegra_car TEGRA30_CLK_SDMMC3>;
+ assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_C>;
+ assigned-clock-rates = <50000000>;
+
+ max-frequency = <50000000>;
keep-power-in-suspend;
bus-width = <4>;
non-removable;
--
2.27.0
