The default parent for all MMCs is PLLP, which is running at 216MHz on
Tegra20 and 50MHz clock can't be derived from PLLP. The maximum SDIO
clock rate is 50MHz, but this rate isn't achievable using PLLP.
Let's switch the WiFi MMC clk parent to PLLC in order to get true 50MHz.
This patch doesn't fix any problems, it's just a minor improvement.
Signed-off-by: Dmitry Osipenko <digetx@xxxxxxxxx>
---
arch/arm/boot/dts/tegra20-acer-a500-picasso.dts | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts
index b89e9398f681..ab3c378e5519 100644
--- a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts
+++ b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts
@@ -744,6 +744,10 @@ mmc@c8000000 {
#address-cells = <1>;
#size-cells = <0>;
+ assigned-clocks = <&tegra_car TEGRA20_CLK_SDMMC1>;
+ assigned-clock-parents = <&tegra_car TEGRA20_CLK_PLL_C>;
+ assigned-clock-rates = <50000000>;
+
max-frequency = <50000000>;
keep-power-in-suspend;
bus-width = <4>;
--
2.27.0
