Set chip->align_buffer_size to 1 for Tegra platforms to make the buffer alignment to be multiple of 128 bytes. This fix is applied as gstreamer alsasink gets stuck with the default buffer-time and latency-time parameters with 4 byte buffer alignment. Signed-off-by: Mohan Kumar <mkumard@xxxxxxxxxx> --- sound/pci/hda/hda_tegra.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/sound/pci/hda/hda_tegra.c b/sound/pci/hda/hda_tegra.c index 5637f0129932..ecf98eb9df36 100644 --- a/sound/pci/hda/hda_tegra.c +++ b/sound/pci/hda/hda_tegra.c @@ -333,6 +333,8 @@ static int hda_tegra_first_init(struct azx *chip, struct platform_device *pdev) gcap = azx_readw(chip, GCAP); dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap); + chip->align_buffer_size = 1; + /* read number of streams from GCAP register instead of using * hardcoded value */ -- 2.17.1
