Tegra HDA has audio data buffer for upto tens of frames, this buffer can help to avoid underflow. HW will keep issuing new data fetch request when buffers are not full and current BDL is not done. When SW disable DMA RUN bit for a stream, HW can't cancel the already issued data fetch request and hence it can't stop DMA. HW has to wait for all issued data fetch request get data returned before it stops DMA. This HW behavior is not in sync with HDA spec which says DMA RUN bit should be cleared within 1 audio frame. For Tegra, DMA RUN bit was active for more than one audio frame, due to this the timeout in snd_hdac_stream_sync function is not helping. When Stream reset set and clear happens during DMA RUN bit active state it results in Memory Decode error. Unfortunately, there is no way to detect when these data accesses have completed, but testing has shown that a 100us delay between Stream reset set and clear operation for Tegra avoids the memory decode error. Therefore, adding a 100us dma stop delay. Signed-off-by: Mohan Kumar <mkumard@xxxxxxxxxx> --- sound/pci/hda/hda_tegra.c | 1 + 1 file changed, 1 insertion(+) diff --git a/sound/pci/hda/hda_tegra.c b/sound/pci/hda/hda_tegra.c index ecf98eb9df36..c94553bcca88 100644 --- a/sound/pci/hda/hda_tegra.c +++ b/sound/pci/hda/hda_tegra.c @@ -308,6 +308,7 @@ static int hda_tegra_first_init(struct azx *chip, struct platform_device *pdev) return err; } bus->irq = irq_id; + bus->dma_stop_delay = 100; card->sync_irq = bus->irq; /* -- 2.17.1
