>> +static irqreturn_t nvidia_smmu_context_fault_bank(int irq, >> + void __iomem *cb_base = nvidia_smmu_page(smmu, inst, >> + smmu->numpage + idx); [...] >> + fsr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSR); [...] >> + writel_relaxed(fsr, cb_base + ARM_SMMU_CB_FSR); >It reads FSR of the default inst (1st), but clears the FSR of corresponding inst -- just want to make sure that this is okay and intended. FSR should be read from corresponding inst. Not from instance 0. Let me post updated patch. -KR
