On Fri, May 15, 2020 at 4:53 PM Thierry Reding <thierry.reding@xxxxxxxxx> wrote:
>
> ----------------------------------------------------------------
> memory: tegra: Changes for v5.8-rc1
>
> Contains a few cleanup patches and an implementation to scale the EMC
> frequency on Tegra210 systems.
I don't mind taking the memory driver patches, but it seems odd that this
pull request has so many drivers/clk changes but does not mention that
in the pull request, and does not Cc the clk maintainers or include Acks
from them.
I would assume that the reason for this is that you have based
the memory controller changes on a branch that was already
accepted by the clk maintainers in to their tree, but when you do that
please be more explicit so I know what is going on.
Waiting for clarification before I can pull this.
Arnd
> Dmitry Osipenko (9):
> dt-bindings: cpufreq: Add binding for NVIDIA Tegra20/30
> clk: tegra: Add custom CCLK implementation
> clk: tegra: pll: Add pre/post rate-change hooks
> clk: tegra: cclk: Add helpers for handling PLLX rate changes
> clk: tegra20: Use custom CCLK implementation
> clk: tegra30: Use custom CCLK implementation
> Joseph Lo (7):
> dt-bindings: memory: tegra: Add external memory controller binding for Tegra210
> clk: tegra: Add PLLP_UD and PLLMB_UD for Tegra210
> clk: tegra: Export functions for EMC clock scaling
> clk: tegra: Implement Tegra210 EMC clock
> clk: tegra: Remove the old emc_mux clock for Tegra210
