Re: [PATCH v5.7] clk: tegra: Fix initial rate for pll_a on Tegra124

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Quoting Thierry Reding (2020-05-05 00:16:55)
> From: Thierry Reding <treding@xxxxxxxxxx>
> 
> pll_a_out0 and the I2S clocks are already configured to default to rates
> corresponding to a 44.1 kHz sampling rate, but the pll_a configuration
> was set to a default that is not listed in the frequency table, which
> caused the PLL code to compute an invalid configuration. As a result of
> this invalid configuration, Jetson TK1 fails to resume from suspend.
> 
> This used to get papered over because the ASoC driver would force audio
> clocks to a 44.1 kHz configuration on boot. However, that's not really
> necessary and was hence removed in commit ff5d18cb04f4 ("ASoC: tegra:
> Enable audio mclk during tegra_asoc_utils_init()").
> 
> Fix the initial rate for pll_a so that it matches the 44.1 kHz entry in
> the pll_a frequency table.
> 
> Fixes: ff5d18cb04f4 ("ASoC: tegra: Enable audio mclk during tegra_asoc_utils_init()")
> Signed-off-by: Thierry Reding <treding@xxxxxxxxxx>
> ---

Applied to clk-fixes




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