On Fri, 3 Apr 2020 22:22:03 +0200, Thierry Reding wrote: > From: Thierry Reding <treding@xxxxxxxxxx> > > The NVIDIA Tegra186 SoC contains an IP block that provides a register > interface for ten timers with a 29-bit counter that can generate one- > shot, periodic or watchdog interrupts. > > Signed-off-by: Thierry Reding <treding@xxxxxxxxxx> > --- > Changes in v2: > - add required properties section > - add additionalProperties: false > - do not show status in example > > .../bindings/timer/nvidia,tegra186-timer.yaml | 61 +++++++++++++++++++ > 1 file changed, 61 insertions(+) > create mode 100644 Documentation/devicetree/bindings/timer/nvidia,tegra186-timer.yaml > Reviewed-by: Rob Herring <robh@xxxxxxxxxx>
