On Thu, Mar 19, 2020 at 1:27 PM Thierry Reding <thierry.reding@xxxxxxxxx> wrote: > From: Thierry Reding <treding@xxxxxxxxxx> > > The GG.0 and GG.1 GPIOs serve as CLKREQ and RST pins, respectively, for > PCIe controller 5 on Tegra194. When this controller is configured in > endpoint mode, these pins need to be used as GPIOs by the PCIe endpoint > driver. Typically the mode programming of these pins (GPIO vs. SFIO) is > performed by early boot firmware to ensure that the configuration is > consistent. > > However, the GG.0 and GG.1 pins are part of a special power partition > that is not enabled during early boot, and hence the early boot firmware > cannot program these pins to be GPIOs (they are SFIO by default). Adding > them as pin ranges for the pin controller allows the pin controller to > be involved when these pins are requested as GPIOs and allows the proper > programming to take place. > > Signed-off-by: Thierry Reding <treding@xxxxxxxxxx> Patch applied! Yours, Linus Walleij
