21.01.2020 19:19, Sowjanya Komatineni пишет:
>
> On 1/19/20 7:04 AM, Dmitry Osipenko wrote:
>> External email: Use caution opening links or attachments
>>
>>
>> 14.01.2020 10:24, Sowjanya Komatineni пишет:
>>
>> [snip]
>>
>>> diff --git a/drivers/clk/tegra/clk-tegra30.c
>>> b/drivers/clk/tegra/clk-tegra30.c
>>> index 5732fdbe20db..53d1c48532ae 100644
>>> --- a/drivers/clk/tegra/clk-tegra30.c
>>> +++ b/drivers/clk/tegra/clk-tegra30.c
>>> @@ -1221,9 +1221,8 @@ static struct tegra_clk_init_table init_table[]
>>> __initdata = {
>>> { TEGRA30_CLK_UARTC, TEGRA30_CLK_PLL_P, 408000000, 0 },
>>> { TEGRA30_CLK_UARTD, TEGRA30_CLK_PLL_P, 408000000, 0 },
>>> { TEGRA30_CLK_UARTE, TEGRA30_CLK_PLL_P, 408000000, 0 },
>>> - { TEGRA30_CLK_PLL_A, TEGRA30_CLK_CLK_MAX, 564480000, 1 },
>>> - { TEGRA30_CLK_PLL_A_OUT0, TEGRA30_CLK_CLK_MAX, 11289600, 1 },
>>> - { TEGRA30_CLK_EXTERN1, TEGRA30_CLK_PLL_A_OUT0, 0, 1 },
>>> + { TEGRA30_CLK_PLL_A, TEGRA30_CLK_CLK_MAX, 564480000, 0 },
>>> + { TEGRA30_CLK_PLL_A_OUT0, TEGRA30_CLK_CLK_MAX, 11289600, 0 },
>>> { TEGRA30_CLK_I2S0, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 },
>>> { TEGRA30_CLK_I2S1, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 },
>>> { TEGRA30_CLK_I2S2, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 },
>>>
>> What about to use the assigned-clock-rates in device-tree and thus to
>> remove those PLL_A entries?
>
> Yes clock rates can be used and also PLL rate is set based on sample
> rate during hw_params. So this can be removed.
>
> But PLLA clock rates are not related to this patch series and also
> changing this needs audio function testing across all platforms and
> currently we don't have audio functional tests in place for older
> platforms.
>
> All audio clocks proper fixes and cleanup b/w clock driver and audio
> driver will be done separately.
If there are real plans to make sound driver to drive the PLLA rate,
then indeed should be fine to keep it as-is for now.
