On Fri, Nov 15, 2019 at 03:34:23PM +0530, Vidya Sagar wrote:
> On 11/15/2019 12:06 AM, Bjorn Helgaas wrote:
> > On Wed, Nov 13, 2019 at 12:20:43PM +0100, Thierry Reding wrote:
> > > On Tue, Nov 12, 2019 at 12:58:44PM -0600, Bjorn Helgaas wrote:
> > >
> > > > My question is whether this wait should be connected somehow with
> > > > platform_pci_set_power_state(). It sounds like the tegra host
> > > > controller driver already does the platform-specific delays, and I'm
> > > > not sure it's reasonable for platform_pci_set_power_state() to do the
> > > > CRS polling. Maybe something like this? I'd really like to get
> > > > Rafael's thinking here.
> > > >
> > > > diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
> > > > index e7982af9a5d8..052fa316c917 100644
> > > > --- a/drivers/pci/pci.c
> > > > +++ b/drivers/pci/pci.c
> > > > @@ -964,9 +964,14 @@ void pci_refresh_power_state(struct pci_dev *dev)
> > > > */
> > > > void pci_power_up(struct pci_dev *dev)
> > > > {
> > > > + pci_power_state_t prev_state = dev->current_state;
> > > > +
> > > > if (platform_pci_power_manageable(dev))
> > > > platform_pci_set_power_state(dev, PCI_D0);
> > > > + if (prev_state == PCI_D3cold)
> > > > + pci_dev_wait(dev, "D3cold->D0", PCIE_RESET_READY_POLL_MS);
>
> Is there any specific reason why should there be a check for the
> state? In Tegra series, I observe that, by the time execution comes
> to this point, prev_state is PCI_D3Hot and in Tegra194 particularly,
> it is PCI_D0 because the host controller driver explicitly keeps the
> downstream devices in PCI_D0 state as a work around for one of the
> Tegra194 specific issues.
I think you're right, we probably should not try to check "prev_state"
here because we can't rely on that being accurate.
On Tegra, I assume suspend puts the PCIe devices in D3hot, then when
we suspend the RC itself, it looks like tegra_pcie_pm_suspend()
actually turns off the power, so the PCIe devices probably go to
D3cold but nothing updates their dev->current_state, so it's probably
still PCI_D3hot.
On Tegra194, the same probably happens, except that when we suspend
the RC itself, tegra_pcie_downstream_dev_to_D0() puts the PCIe devices
back in D0 (updating their dev->current_state to PCI_D0), and then we
turn off the power, so they probably also end up in D3cold but with
dev_current_state still set to PCI_D0.
> So, I feel the check for current_state may not be need here(?)
I think you're right. We can't tell what dev->current_state is when
we enter pci_power_up().
Bjorn
