On Thu, Nov 14, 2019 at 02:29:51PM +0300, Dmitry Osipenko wrote: > 14.11.2019 02:03, Stephen Boyd пишет: > > Quoting Dmitry Osipenko (2019-10-29 17:48:13) > >> UART clock is divided using divisor values from DLM/DLL registers when > >> enable-bit is unset in clk register and clk's divider configuration isn't > >> taken onto account in this case. This doesn't cause any problems, but > >> let's add a check for the divider's enable-bit state, for consistency. > >> > >> Acked-by: Peter De Schrijver <pdeschrijver@xxxxxxxxxx> > >> Signed-off-by: Dmitry Osipenko <digetx@xxxxxxxxx> > >> --- > > > > Is this going to be picked up or should I just apply atop the tegra PR? > > Looks like this patch missed the Tegra's PR by accident. > > Stephen, I assume it will be easier if you could apply this patch atop. > The patch doesn't have any dependencies on any other patches, so it's > fine to apply it separately. Thanks in advance! > > Thierry, please let us know if you have any objections. It's not so much that I missed to pick this up. It's just that it didn't make it in time. This was posted just a couple of days before v5.4-rc6 and I had already finalized the branches at that point. Given that this doesn't fix any actual issues it didn't seem worth to force it in at that point. That said, I don't have any objections if Stephen wants to pick this up on top of the pull requests. Thierry
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