[GIT PULL 2/2] clk: tegra: Changes for v5.5-rc1

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Hi Michael, Stephen,

The following changes since commit 54ecb8f7028c5eb3d740bb82b0f1d90f2df63c5c:

  Linux 5.4-rc1 (2019-09-30 10:35:40 -0700)

are available in the Git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux.git tags/tegra-for-5.5-clk

for you to fetch changes up to 25c6fa38444d1bad287895447a17a3cfdbaeee10:

  clk: tegra: Fix build error without CONFIG_PM_SLEEP (2019-11-01 10:44:52 +0100)

Thanks,
Thierry

----------------------------------------------------------------
clk: tegra: Changes for v5.5-rc1

The bulk of these changes implement suspend/resume support for Tegra210.
In addition, some of the SOR clocks on earlier Tegra generations are
reimplemented to more closely match the implementation on later chips,
which in turn makes it possible to handle HDMI and DP support in a more
unified way.

----------------------------------------------------------------
Dmitry Osipenko (3):
      clk: tegra: Add Tegra20/30 EMC clock implementation
      clk: tegra: Optimize PLLX restore on Tegra20/30
      clk: tegra: Add missing stubs for the case of !CONFIG_PM_SLEEP

Sowjanya Komatineni (12):
      clk: Add API to get index of the clock parent
      clk: tegra: divider: Save and restore divider rate
      clk: tegra: pllout: Save and restore pllout context
      clk: tegra: pll: Save and restore pll context
      clk: tegra: Support for OSC context save and restore
      clk: tegra: periph: Add restore_context support
      clk: tegra: clk-super: Fix to enable PLLP branches to CPU
      clk: tegra: clk-super: Add restore-context support
      clk: tegra: clk-dfll: Add suspend and resume support
      clk: tegra: Use fence_udelay() during PLLU init
      clk: tegra: Share clk and rst register defines with Tegra clock driver
      clk: tegra: Add suspend and resume support on Tegra210

Thierry Reding (8):
      dt-bindings: clock: tegra: Rename SOR0_LVDS to SOR0_OUT
      Merge branch 'for-5.5/clk-core'
      Merge branch 'for-5.5/dt-bindings'
      clk: tegra: Remove last remains of TEGRA210_CLK_SOR1_SRC
      clk: tegra: Move SOR0 implementation to Tegra124
      clk: tegra: Rename sor0_lvds to sor0_out
      clk: tegra: Reimplement SOR clock on Tegra124
      clk: tegra: Reimplement SOR clocks on Tegra210

YueHaibing (1):
      clk: tegra: Fix build error without CONFIG_PM_SLEEP

 drivers/clk/clk.c                               |  17 ++
 drivers/clk/tegra/Makefile                      |   2 +
 drivers/clk/tegra/clk-dfll.c                    |  56 +++++
 drivers/clk/tegra/clk-dfll.h                    |   2 +
 drivers/clk/tegra/clk-divider.c                 |  11 +
 drivers/clk/tegra/clk-id.h                      |   4 +-
 drivers/clk/tegra/clk-periph.c                  |  18 ++
 drivers/clk/tegra/clk-pll-out.c                 |   9 +
 drivers/clk/tegra/clk-pll.c                     |  86 ++++---
 drivers/clk/tegra/clk-sdmmc-mux.c               |  12 +
 drivers/clk/tegra/clk-super.c                   |  35 +++
 drivers/clk/tegra/clk-tegra-fixed.c             |  15 ++
 drivers/clk/tegra/clk-tegra-periph.c            |   8 -
 drivers/clk/tegra/clk-tegra-super-gen4.c        |   7 +-
 drivers/clk/tegra/clk-tegra124-dfll-fcpu.c      |   1 +
 drivers/clk/tegra/clk-tegra124.c                |  55 ++++-
 drivers/clk/tegra/clk-tegra20-emc.c             | 293 ++++++++++++++++++++++++
 drivers/clk/tegra/clk-tegra20.c                 |  80 +++----
 drivers/clk/tegra/clk-tegra210.c                | 181 ++++++++++++---
 drivers/clk/tegra/clk-tegra30.c                 |  63 +++--
 drivers/clk/tegra/clk.c                         | 112 +++++----
 drivers/clk/tegra/clk.h                         |  70 ++++++
 include/dt-bindings/clock/tegra124-car-common.h |   3 +-
 include/dt-bindings/clock/tegra210-car.h        |   6 +-
 include/linux/clk-provider.h                    |   1 +
 include/linux/clk/tegra.h                       |  24 ++
 26 files changed, 983 insertions(+), 188 deletions(-)
 create mode 100644 drivers/clk/tegra/clk-tegra20-emc.c



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