On Wed, Sep 25, 2019 at 01:38:51PM +0200, Thierry Reding wrote:
> From: Thierry Reding <treding@xxxxxxxxxx>
>
> The EQOS hardware block found on Tegra194 is in fact not compatible with
> the instantiation on Tegra186. While the register programming is exactly
> the same, one notable difference is that on Tegra194 only 39 bits out of
> the advertised 40 bits can be used. Bit 39 enables some on-the-fly
> swizzling of data that is counter-productive to ethernet connectivity.
>
> Signed-off-by: Thierry Reding <treding@xxxxxxxxxx>
> ---
> arch/arm64/boot/dts/nvidia/tegra194.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
It turns out that the EQOS controller is perfectly capable of addressing
40 bits of system memory. The fact that bit 39 is special is a system-
level detail that is better described by restricting the DMA mask using
a dma-ranges property. Patches to do that will follow.
Instead I've replaced this patch with one that adds nvidia,tegra194-eqos
in addition to the nvidia,tegra186-eqos compatible string. This follows
the established practice of always listing the SoC-specific compatible
string, even if the hardware is compatible with prior generations. This
is to make sure workarounds for unforeseen bugs and incompatibilities
can be implemented in an OS when matching on the specific compatible
string.
Thierry
>
> diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
> index e590a3cebed0..49e2121f0cbf 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
> @@ -40,7 +40,7 @@
> };
>
> ethernet@2490000 {
> - compatible = "nvidia,tegra186-eqos",
> + compatible = "nvidia,tegra194-eqos",
> "snps,dwc-qos-ethernet-4.10";
> reg = <0x02490000 0x10000>;
> interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
> --
> 2.23.0
>
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