On 16/09/2019 09:37, Sameer Pujar wrote:
> From Tegra186 onwards OUTSTANDING_REQUESTS field is added in channel
> configuration register(bits 7:4) which defines the maximum number of reads
> from the source and writes to the destination that may be outstanding at
> any given point of time. This field must be programmed with a value
> between 1 and 8. A value of 0 will prevent any transfers from happening.
>
> Thus added 'has_outstanding_reqs' bool member in chip data structure and is
> set to false for Tegra210, since the field is not applicable. For Tegra186
> it is set to true and channel configuration is updated with maximum
> outstanding requests.
>
> Fixes: 433de642a76c ("dmaengine: tegra210-adma: add support for Tegra186/Tegra194")
> Cc: stable@xxxxxxxxxxxxxxx
>
> Signed-off-by: Sameer Pujar <spujar@xxxxxxxxxx>
> ---
> drivers/dma/tegra210-adma.c | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/drivers/dma/tegra210-adma.c b/drivers/dma/tegra210-adma.c
> index 5f8adf5..e19732f 100644
> --- a/drivers/dma/tegra210-adma.c
> +++ b/drivers/dma/tegra210-adma.c
> @@ -66,6 +66,8 @@
> #define TEGRA186_FIFO_CTRL_DEFAULT (TEGRA186_ADMA_CH_FIFO_CTRL_TXSIZE(3) | \
> TEGRA186_ADMA_CH_FIFO_CTRL_RXSIZE(3))
>
> +#define TEGRA186_ADMA_CH_CONFIG_OUTSTANDING_REQS(reqs) (reqs << 4)
> +
Shouldn't we place this under the defines for ADMA_CH_CONFIG register?
This would be consistent with how we organise the definitions today.
> #define ADMA_CH_REG_FIELD_VAL(val, mask, shift) (((val) & mask) << shift)
>
> struct tegra_adma;
> @@ -77,6 +79,7 @@ struct tegra_adma;
> * @ch_req_tx_shift: Register offset for AHUB transmit channel select.
> * @ch_req_rx_shift: Register offset for AHUB receive channel select.
> * @ch_base_offset: Register offset of DMA channel registers.
> + * @has_outstanding_reqs: If DMA channel can have outstanding requests.
> * @ch_fifo_ctrl: Default value for channel FIFO CTRL register.
> * @ch_req_mask: Mask for Tx or Rx channel select.
> * @ch_req_max: Maximum number of Tx or Rx channels available.
> @@ -95,6 +98,7 @@ struct tegra_adma_chip_data {
> unsigned int ch_req_max;
> unsigned int ch_reg_size;
> unsigned int nr_channels;
> + bool has_outstanding_reqs;
> };
>
> /*
> @@ -594,6 +598,8 @@ static int tegra_adma_set_xfer_params(struct tegra_adma_chan *tdc,
> ADMA_CH_CTRL_FLOWCTRL_EN;
> ch_regs->config |= cdata->adma_get_burst_config(burst_size);
> ch_regs->config |= ADMA_CH_CONFIG_WEIGHT_FOR_WRR(1);
> + if (cdata->has_outstanding_reqs)
> + ch_regs->config |= TEGRA186_ADMA_CH_CONFIG_OUTSTANDING_REQS(8);
> ch_regs->fifo_ctrl = cdata->ch_fifo_ctrl;
> ch_regs->tc = desc->period_len & ADMA_CH_TC_COUNT_MASK;
>
> @@ -778,6 +784,7 @@ static const struct tegra_adma_chip_data tegra210_chip_data = {
> .ch_req_tx_shift = 28,
> .ch_req_rx_shift = 24,
> .ch_base_offset = 0,
> + .has_outstanding_reqs = false,
> .ch_fifo_ctrl = TEGRA210_FIFO_CTRL_DEFAULT,
> .ch_req_mask = 0xf,
> .ch_req_max = 10,
> @@ -792,6 +799,7 @@ static const struct tegra_adma_chip_data tegra186_chip_data = {
> .ch_req_tx_shift = 27,
> .ch_req_rx_shift = 22,
> .ch_base_offset = 0x10000,
> + .has_outstanding_reqs = true,
> .ch_fifo_ctrl = TEGRA186_FIFO_CTRL_DEFAULT,
> .ch_req_mask = 0x1f,
> .ch_req_max = 20,
>
Otherwise ...
Acked-by: Jon Hunter <jonathanh@xxxxxxxxxx>
Cheers
Jon
--
nvpublic
