On Mon, Aug 19, 2019 at 01:09:18PM +0100, Will Deacon wrote: > On Mon, Aug 19, 2019 at 01:28:56PM +0200, Thierry Reding wrote: > > Perhaps an alternative would be to add a property to the SMMU node that > > lists a set of stream IDs for which to enable bypass by default. We > > could let the firmware set that when the display hardware has been set > > up. That way when the kernel boots we can keep scanning from the > > reserved memory and the ARM SMMU driver would not disable bypass for the > > display hardware. Only when the display hardware is actually attached to > > the IOMMU domain, and the 1:1 mappings have been created would bypass be > > disabled, and at that point there should be no SMMU faults anymore, so > > we have cleanly transitioned to the kernel. > > > > Any thoughts? > > There is currently an extension to IORT under discussion which should > address this problem, so it would make a lot of sense for the DT solution > to follow the same approach. I think it will end up being along the lines > that you suggest, although we won't just enable bypass because that leaves > memory wide open if the device driver doesn't probe and it also creates > an issue because device attach typically happens before the endpoint > driver has probed. > > So the flow would look something like: > > - Firmware describes a physical region of memory which must be > reserved by the OS. > > - Additionally, firmware describes a master -> reserved memory > linkage as part of the IOMMU description. > > - When the IOMMU probes, these reserved memory regions will be > mapped 1:1 for the relevant master. > > This is similar to RMRR on x86, except that the mappings are intended to > be less rigid and can be torn down if the endpoint driver decides to do > that or for things like device passthrough. > > If we get that working, we should update our booting.txt so that DMA is > allowed during boot in the limited cases which this covers. Hi Will, that sounds very interesting. Is this extension being publicly discussed? If so, do you have any pointers for me to read up on this? As for device tree, I wonder if perhaps we can achieve this without going through extra properties. We could, for example, just do a "reverse lookup" of IOMMU masters by walking the device tree and looking for nodes that link to an ARM SMMU in their iommus property. Granted, that's not going to be very efficient, but it would remove the need to duplicate information in DT. It's also going to be a one-time cost, so perhaps it would be negligible. I'm happy to help out with hashing out or implementing something on the DT side of things. I don't currently have access to any systems with ACPI, but I've got a bunch of systems that are DT based and that I would like to see this implemented on. Thierry
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