09.08.2019 2:46, Sowjanya Komatineni пишет: > This patch uses fence_udelay rather than udelay during PLLU > initialization to ensure writes to clock registers happens before > waiting for specified delay. > > Acked-by: Thierry Reding <treding@xxxxxxxxxx> > Signed-off-by: Sowjanya Komatineni <skomatineni@xxxxxxxxxx> > --- > drivers/clk/tegra/clk-tegra210.c | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c > index 4721ee030d1c..998bf60b219a 100644 > --- a/drivers/clk/tegra/clk-tegra210.c > +++ b/drivers/clk/tegra/clk-tegra210.c > @@ -2841,7 +2841,7 @@ static int tegra210_enable_pllu(void) > reg = readl_relaxed(clk_base + pllu.params->ext_misc_reg[0]); > reg &= ~BIT(pllu.params->iddq_bit_idx); > writel_relaxed(reg, clk_base + pllu.params->ext_misc_reg[0]); > - udelay(5); > + fence_udelay(5, clk_base); > > reg = readl_relaxed(clk_base + PLLU_BASE); > reg &= ~GENMASK(20, 0); > @@ -2849,7 +2849,7 @@ static int tegra210_enable_pllu(void) > reg |= fentry->n << 8; > reg |= fentry->p << 16; > writel(reg, clk_base + PLLU_BASE); > - udelay(1); > + fence_udelay(1, clk_base); > reg |= PLL_ENABLE; > writel(reg, clk_base + PLLU_BASE); > > @@ -2895,12 +2895,12 @@ static int tegra210_init_pllu(void) > reg = readl_relaxed(clk_base + XUSB_PLL_CFG0); > reg &= ~XUSB_PLL_CFG0_PLLU_LOCK_DLY_MASK; > writel_relaxed(reg, clk_base + XUSB_PLL_CFG0); > - udelay(1); > + fence_udelay(1, clk_base); > > reg = readl_relaxed(clk_base + PLLU_HW_PWRDN_CFG0); > reg |= PLLU_HW_PWRDN_CFG0_SEQ_ENABLE; > writel_relaxed(reg, clk_base + PLLU_HW_PWRDN_CFG0); > - udelay(1); > + fence_udelay(1, clk_base); > > reg = readl_relaxed(clk_base + PLLU_BASE); > reg &= ~PLLU_BASE_CLKENABLE_USB; > The clk_base corresponds to the RESET controller's part of Clock-and-Reset hardware, is it okay to read-back the RST register and not the clock for the fencing?
