From: Robin Murphy <robin.murphy@xxxxxxx> Date: Jul/23/2019, 11:29:28 (UTC+00:00) > On 23/07/2019 11:07, Jose Abreu wrote: > > From: Jon Hunter <jonathanh@xxxxxxxxxx> > > Date: Jul/23/2019, 11:01:24 (UTC+00:00) > > > >> This appears to be a winner and by disabling the SMMU for the ethernet > >> controller and reverting commit 954a03be033c7cef80ddc232e7cbdb17df735663 > >> this worked! So yes appears to be related to the SMMU being enabled. We > >> had to enable the SMMU for ethernet recently due to commit > >> 954a03be033c7cef80ddc232e7cbdb17df735663. > > > > Finally :) > > > > However, from "git show 954a03be033c7cef80ddc232e7cbdb17df735663": > > > > + There are few reasons to allow unmatched stream bypass, and > > + even fewer good ones. If saying YES here breaks your board > > + you should work on fixing your board. > > > > So, how can we fix this ? Is your ethernet DT node marked as > > "dma-coherent;" ? > > The first thing to try would be booting the failing setup with > "iommu.passthrough=1" (or using CONFIG_IOMMU_DEFAULT_PASSTHROUGH) - if > that makes things seem OK, then the problem is likely related to address > translation; if not, then it's probably time to start looking at nasties > like coherency and ordering, although in principle I wouldn't expect the > SMMU to have too much impact there. > > Do you know if the SMMU interrupts are working correctly? If not, it's > possible that an incorrect address or mapping direction could lead to > the DMA transaction just being silently terminated without any fault > indication, which generally presents as inexplicable weirdness (I've > certainly seen that on another platform with the mix of an unsupported > interrupt controller and an 'imperfect' ethernet driver). > > Just to confirm, has the original patch been tested with > CONFIG_DMA_API_DEBUG to rule out any high-level mishaps? Yes but both my setups don't have any IOMMU: One is x86 + SWIOTLB and another is just coherent regarding CPU. --- Thanks, Jose Miguel Abreu
