On 19. 7. 8. 오전 7:33, Dmitry Osipenko wrote: > Increase sampling period by 4ms to get a nicer pow2 value, converting > diving into shifts in the code. That's more preferable for Tegra30 that > doesn't have hardware divider instructions because of older Cortex-A9 CPU. > In a result boosting events are delayed by 4ms, which is not sensible in > practice at all. > > Signed-off-by: Dmitry Osipenko <digetx@xxxxxxxxx> > --- > drivers/devfreq/tegra30-devfreq.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/devfreq/tegra30-devfreq.c b/drivers/devfreq/tegra30-devfreq.c > index 19e872a64148..bde19b758643 100644 > --- a/drivers/devfreq/tegra30-devfreq.c > +++ b/drivers/devfreq/tegra30-devfreq.c > @@ -71,7 +71,7 @@ > * translates to 2 ^ (K_VAL + 1). ex: 2 ^ (6 + 1) = 128 > */ > #define ACTMON_AVERAGE_WINDOW_LOG2 6 > -#define ACTMON_SAMPLING_PERIOD 12 /* ms */ > +#define ACTMON_SAMPLING_PERIOD 16 /* ms */ > > #define KHZ 1000 > > Reviewed-by: Chanwoo Choi <cw00.choi@xxxxxxxxxxx> -- Best Regards, Chanwoo Choi Samsung Electronics
