Machine hangs after entering LP2 if EMC clock is running off the PLLP.
Either hardware is touching PLLP during LP2, making it unstable, or there
is a software bug somewhere around PLLP programming. Real reason is
unknown, hence let's simply avoid LP2 for CPU0 for now to workaround the
problem. Note that LP2 works fine when EMC is running off any other parent
clock, LP1 is totally unaffected. Also note that there is no hang on LP2
if memory timing is set up for a higher rate (600MHz) when on PLLP, which
makes this extra suspicious.
Signed-off-by: Dmitry Osipenko <digetx@xxxxxxxxx>
---
arch/arm/mach-tegra/cpuidle-tegra30.c | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-tegra/cpuidle-tegra30.c b/arch/arm/mach-tegra/cpuidle-tegra30.c
index c6128526877d..0f8da69ba5be 100644
--- a/arch/arm/mach-tegra/cpuidle-tegra30.c
+++ b/arch/arm/mach-tegra/cpuidle-tegra30.c
@@ -60,10 +60,15 @@ static bool tegra30_cpu_cluster_power_down(struct cpuidle_device *dev,
struct cpuidle_driver *drv,
int index)
{
- /* All CPUs entering LP2 is not working.
+ /*
+ * All CPUs entering LP2 is not working.
* Don't let CPU0 enter LP2 when any secondary CPU is online.
+ *
+ * Machine hangs after entering LP2 if EMC is running off PLLP,
+ * reason is unknown.
*/
- if (num_online_cpus() > 1 || !tegra_cpu_rail_off_ready()) {
+ if (num_online_cpus() > 1 || !tegra_cpu_rail_off_ready() ||
+ tegra20_clk_emc_on_pllp()) {
cpu_do_idle();
return false;
}
--
2.22.0
