From: Dmitry Osipenko <digetx@xxxxxxxxx>
Reset timer's hardware state to ensure that initially it is in a
predictable state.
Signed-off-by: Dmitry Osipenko <digetx@xxxxxxxxx>
Acked-By: Peter De Schrijver <pdeschrijver@xxxxxxxxxx>
Signed-off-by: Daniel Lezcano <daniel.lezcano@xxxxxxxxxx>
---
drivers/clocksource/timer-tegra20.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/clocksource/timer-tegra20.c b/drivers/clocksource/timer-tegra20.c
index acd68c77fa91..3e4f12aee8df 100644
--- a/drivers/clocksource/timer-tegra20.c
+++ b/drivers/clocksource/timer-tegra20.c
@@ -123,6 +123,9 @@ static int tegra_timer_setup(unsigned int cpu)
{
struct timer_of *to = per_cpu_ptr(&tegra_to, cpu);
+ writel(0, timer_of_base(to) + TIMER_PTV);
+ writel(TIMER_PCR_INTR_CLR, timer_of_base(to) + TIMER_PCR);
+
irq_force_affinity(to->clkevt.irq, cpumask_of(cpu));
enable_irq(to->clkevt.irq);
--
2.17.1
