Quoting JC Kuo (2019-06-11 20:14:34)
> Full-speed and low-speed USB devices do not work with Tegra210
> platforms because of incorrect PLLU/PLLU_OUT1 clock settings.
>
> When full-speed device is connected:
> [ 14.059886] usb 1-3: new full-speed USB device number 2 using tegra-xusb
> [ 14.196295] usb 1-3: device descriptor read/64, error -71
> [ 14.436311] usb 1-3: device descriptor read/64, error -71
> [ 14.675749] usb 1-3: new full-speed USB device number 3 using tegra-xusb
> [ 14.812335] usb 1-3: device descriptor read/64, error -71
> [ 15.052316] usb 1-3: device descriptor read/64, error -71
> [ 15.164799] usb usb1-port3: attempt power cycle
>
> When low-speed device is connected:
> [ 37.610949] usb usb1-port3: Cannot enable. Maybe the USB cable is bad?
> [ 38.557376] usb usb1-port3: Cannot enable. Maybe the USB cable is bad?
> [ 38.564977] usb usb1-port3: attempt power cycle
>
> This commit fixes the issue by:
> 1. initializing PLLU_OUT1 before initializing XUSB_FS_SRC clock
> because PLLU_OUT1 is parent of XUSB_FS_SRC.
> 2. changing PLLU post-divider to /2 (DIVP=1) according to Technical
> Reference Manual.
>
> Fixes: e745f992cf4b ("clk: tegra: Rework pll_u")
> Signed-off-by: JC Kuo <jckuo@xxxxxxxxxx>
> ---
Applied to clk-next
