On Tue, Jun 18, 2019 at 05:03:53PM +0300, Dmitry Osipenko wrote: > The of_clk structure has a period field that is set up initially by > timer_of_clk_init(), that period value need to be adjusted for a case of > TIMER1-9 that are running at a fixed rate that doesn't match the clock's > rate. Note that the period value is currently used only by some of the > clocksource drivers internally and hence this is just a minor cleanup > change that doesn't fix anything. > > Signed-off-by: Dmitry Osipenko <digetx@xxxxxxxxx> > --- > drivers/clocksource/timer-tegra.c | 5 +++-- > 1 file changed, 3 insertions(+), 2 deletions(-) Acked-by: Thierry Reding <treding@xxxxxxxxxx>
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