On 18/06/2019 15:03, Dmitry Osipenko wrote:
> Tegra's timer uses n+1 scheme for the counter, i.e. timer will fire after
> one tick if 0 is loaded. The minimum and maximum numbers of oneshot ticks
> are defined by clockevents_config_and_register(min, max) invocation and
> the min value is set to 1 tick. Hence "cycles" value can't ever be 0,
> unless it's a bug in clocksource core.
>
> Signed-off-by: Dmitry Osipenko <digetx@xxxxxxxxx>
> ---
> drivers/clocksource/timer-tegra.c | 13 ++++++++++---
> 1 file changed, 10 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/clocksource/timer-tegra.c b/drivers/clocksource/timer-tegra.c
> index 2673b6e0caa8..b84324288749 100644
> --- a/drivers/clocksource/timer-tegra.c
> +++ b/drivers/clocksource/timer-tegra.c
> @@ -54,9 +54,16 @@ static int tegra_timer_set_next_event(unsigned long cycles,
> {
> void __iomem *reg_base = timer_of_base(to_timer_of(evt));
>
> - writel_relaxed(TIMER_PTV_EN |
> - ((cycles > 1) ? (cycles - 1) : 0), /* n+1 scheme */
> - reg_base + TIMER_PTV);
> + /*
> + * Tegra's timer uses n+1 scheme for the counter, i.e. timer will
> + * fire after one tick if 0 is loaded.
> + *
> + * The minimum and maximum numbers of oneshot ticks are defined
> + * by clockevents_config_and_register(1, 0x1fffffff + 1) invocation
> + * below in the code. Hence the cycles (ticks) can't be outside of
> + * a range supportable by hardware.
> + */
> + writel_relaxed(TIMER_PTV_EN | (cycles - 1), reg_base + TIMER_PTV);
>
> return 0;
> }
>
Acked-by: Jon Hunter <jonathanh@xxxxxxxxxx>
Cheers
Jon
--
nvpublic
