On 13/06/2019 17:12, Thierry Reding wrote:
> From: Thierry Reding <treding@xxxxxxxxxx>
>
> A PLL in IDDQ doesn't work, whether it's enabled or not. This is not a
> configuration that makes sense, so warn about it.
>
> Signed-off-by: Thierry Reding <treding@xxxxxxxxxx>
> ---
> drivers/clk/tegra/clk-tegra210.c | 6 +++++-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
> index 4904ac4a75db..793c7acaf4e2 100644
> --- a/drivers/clk/tegra/clk-tegra210.c
> +++ b/drivers/clk/tegra/clk-tegra210.c
> @@ -1003,8 +1003,12 @@ static void tegra210_pllre_set_defaults(struct tegra_clk_pll *pllre)
> _pll_misc_chk_default(clk_base, pllre->params, 0, val,
> ~mask & PLLRE_MISC0_WRITE_MASK);
>
> - /* Enable lock detect */
> + /* The PLL doesn't work if it's in IDDQ. */
> val = readl_relaxed(clk_base + pllre->params->ext_misc_reg[0]);
> + if (val & PLLRE_MISC0_IDDQ)
> + pr_warn("unexpected IDDQ bit set for enabled clock\n");
> +
> + /* Enable lock detect */
> val &= ~mask;
> val |= PLLRE_MISC0_DEFAULT_VALUE & mask;
> writel_relaxed(val, clk_base + pllre->params->ext_misc_reg[0]);
Looks like there are a few other instances of this that could be fixed
as well.
Acked-by: Jon Hunter <jonathanh@xxxxxxxxxx>
Cheers
Jon
--
nvpublic
