On 10/06/2019 17:44, Dmitry Osipenko wrote: > We're adjusting the timer's base for each per-CPU timer to point to the > actual start of the timer since device-tree defines a compound registers > range that includes all of the timers. In this case the original base > need to be restore before calling iounmap to unmap the proper address. > > Signed-off-by: Dmitry Osipenko <digetx@xxxxxxxxx> > --- > drivers/clocksource/timer-tegra.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/clocksource/timer-tegra.c b/drivers/clocksource/timer-tegra.c > index 2a428fdf702f..7be91db98bd7 100644 > --- a/drivers/clocksource/timer-tegra.c > +++ b/drivers/clocksource/timer-tegra.c > @@ -345,6 +345,8 @@ static int __init tegra_init_timer(struct device_node *np, bool tegra20, > irq_dispose_mapping(cpu_to->clkevt.irq); > } > } > + > + to->of_base.base = timer_reg_base; > out: > timer_of_cleanup(to); So what you are saying is that because we don't know which CPU executes the tegra_init_timer() function, then it is necessary to restore the base. IOW if it is not CPU0, then the base will be updated and hence, need to be restored. Correct? Jon -- nvpublic
