On 25/04/2019 00:17, Dmitry Osipenko wrote: > The readl/writel functions are inserting memory barrier in order to > ensure that memory stores are completed. On Tegra20 and Tegra30 this > results in L2 cache syncing which isn't a cheapest operation. The > tegra20-apb-dma driver doesn't need to synchronize generic memory > accesses, hence use the relaxed versions of the functions. Do you mean device-io accesses here as this is not generic memory? Although there may not be any issues with this change, I think I need a bit more convincing that we should do this given that we have had it this way for sometime and I would not like to see us introduce any regressions as this point without being 100% certain we would not. Ideally, if I had some good extensive tests I could run to hammer the DMA for all configurations with different combinations of channels running simultaneously then we could test this, but right now I don't :-( Have you ... 1. Tested both cyclic and scatter-gather transfers? 2. Stress tested simultaneous transfers with various different configurations? 3. Quantified the actual performance benefit of this change so we can understand how much of a performance boost this offers? Cheers Jon
